In a field of optical communication network, to establish future multimedia network, there has been demand for an optical communication apparatus which provides high-speed communication with great capacity. To realize the high-speed communication with great capacity, an optical packet switching system using a high-speed optical switch which works on the order of nanoseconds (ns) has been researched and developed. An SOA (Semiconductor Optical Amplifier) with which high-speed switching on the order of nanoseconds is realized is expected to be applied to a matrix optical switch and the like in the optical packet switching system.
FIG. 3 depicts an illustration of the optical packet switching system. As depicted in FIG. 3, the optical packet switching system includes edge nodes 1 to 10, and core nodes 11 to 14. The edge nodes 1 to 10 are devices which relay optical packet signals transmitted between the optical packet switching network and other access networks.
The core nodes 11 to 14 have a matrix optical switch function which switches routes (optical routes) of the optical packet signals. FIG. 4 depicts a functional block diagram which depicts configuration of the conventional core node 11 (the core nodes 12 to 14 have the same configuration). As depicted in FIG. 4, the core node 11 includes wavelength converters 20 to 23, a matrix optical switch 24, a control unit (Reservation manager) 25, and an O/E/O (Optical to Electrical to Optical) converter 26.
Of the configuration above, the wavelength converters 20 to 23 convert the wavelength of the optical packet signal. The matrix optical switch 24 switches routes of the optical packet signals based on a control signal input from the control unit (Reservation manager) 25.
The control unit 25 controls the matrix optical switch 24 based on a label signal input from the O/E/O converter 26. The label signal includes route information of the optical packet signal.
The O/E/O converter 26 converts the optical signal input from an outside into an electrical signal, and outputs the label signal included in the converted signal to the control unit 25. After the O/E/O converter converts the electric signal back into the optical signal, the O/E/O converter 26 outputs the converted optical signal to an outside.
FIG. 5 depicts an illustration of switching timing of the optical packet signal. FIG. 5 schematically depicts the optical signal moving to right. As depicted in FIG. 5, the matrix optical switch 24 is switched at a certain interval offset time after the label signal. Switching the matrix optical switch needs to be completed during time between transit time (about ions; optical switch switching time) of an optical packet signal A and that of an optical packet signal B.
A configuration of the matrix optical switch 24 depicted in FIG. 4 is described. As depicted in FIG. 4, the matrix optical switch 24 includes division couplers 30a to 30c, multiplexing couplers 40a to 40c, and an SOA (an SOA-gate optical switch) 40.
Each of the division couplers 30a to 30c divides input optical packet signals, and each of the multiplexing couplers 40a to 40c multiplexes input optical signals. The SOA 40 switches a route of a desired optical packet signal by turning on or turning off drive current which is input from an outside.
The following describes a case in FIG. 6 where an optical packet signal #n which is input to an input port #1 of the division coupler 30a is output to an output port #n. The optical packet signal #n is divided into n signals at the division coupler 30a, and each of the divided n optical packet signals is input to each of the SOAs 40 corresponding to each of the output ports.
As the optical packet signal #n is output to the output port #n, one of the SOAs 40 receiving the output from the division coupler 30a, corresponding to the output port #n is turned on, whereas the other SOAs 40 corresponding to other output ports are turned off, whereby the optical packet signal #n is output from the input port #1 to the output port #n.
An operation of the SOA 40 depicted in FIG. 6 is described below. FIG. 7 depicts an illustration of the operation of the SOA 40. FIG. 7 depicts the SOA 40, and a drive circuit 45 which drives the SOA 40. Further, (a) in FIG. 7 is the optical packet signal which is input into the SOA 40, (b) in FIG. 7 is drive current supplied from the drive circuit 45 for the SOA 40, and (c) in FIG. 7 is the optical packet signal which is output to the SOA 40.
The control signal is input into the drive circuit 45. Based on the control signal, the drive circuit 45 outputs the drive current depicted by (b) in FIG. 7 to the SOA 40. As the drive current from the drive circuit 45 is applied to an optical-signal amplifying region, the SOA 40 amplifies the optical signal propagating the amplifying region. The SOA 40 is used as a gate device which turns the drive current on and off as depicted by (b) in FIG. 7.
For example, when the drive current of timing depicted by (b) in FIG. 7 is applied, the SOA 40 turns on the gate for the optical packet signals #1, #3 of the optical packet signals #1 to #3 depicted by (a) in FIG. 7, and turns off the gate for the optical signal #2. Accordingly, the SOA 40 outputs the optical packet signal depicted by (c) in FIG. 7.
A relation between the drive current and optical gain of the SOA 40 is described. FIG. 8 depicts the relation between the drive current and the optical gain of the SOA 40. The SOA 40 is a semiconductor optical amplifier which is configured such that the optical gain changes depending on the drive current. In FIG. 8, for example, when a drive current of 300 mA is applied, the optical gain becomes saturated at approximately 10 dB. On the other hand, when the drive current is low, the SOA 40 depicts optical attenuation characteristics.
A relation between the drive voltage and the optical gain of the SOA 40 is described. FIG. 9 depicts the relation between the drive voltage and the optical gain of the SOA 40. The SOA 40 is driven by current, and further, the SOA 40 may be driven by voltage by applying voltage thereto from voltage source which can apply a current of 300 mA or more. In FIG. 9, when about a voltage of 1.5 V is applied as voltage source, about a drive current of 300 mA is applied to the SOA. On the other hand, when the drive voltage is low, the SOA 40 depicts the optical attenuation characteristics.
A relation between the drive voltage and an extinction ratio of the SOA 40 is described (extinction ratio between the semiconductor optical amplifying gate switches). FIG. 10 depicts the relation between the drive voltage and the extinction ratio of the SOA 40. In the configuration of the matrix optical switch 24 (see FIG. 6), the input ports of the multiplexing couplers 40a to 40c are connected with the SOAs 40 of the same number, respectively. When one of the SOAs 40 connected with a certain multiplexing coupler is turned on, the rest of the SOAs 40 are turned off.
Even when the SOA 40 is turned off, some light leaks out of the SOA 40, and causes optical crosstalk at the multiplexing coupler. FIG. 10 depicts the optical crosstalk in graph form of the extinction ratio characteristics. For example, to set up the 8×8 matrix optical switch, the extinction ratio characteristics between on state and off state need to be approximately 58 dB (crosstalk occurs when the extinction ratio characteristics are more than or equal to 58 dB). To achieve the extinction ratio characteristics, the drive current of the SOA 40 which is turned off needs to be set at 0.65 V or less (the extinction ratio becomes 58 dB or more when the drive current is set at 0.65 V or less).
An example circuit of the drive circuit 45 depicted in FIG. 7 is described. FIG. 11 depicts the example circuit of the conventional drive circuit 45. AS depicted in FIG. 11, the drive circuit 45 includes the resistors R51 to R53, operational amplifiers OP51 to OP53, buffers BUF51 and BUF52, an inverter INV51, transistors (high-speed transistors) FET51 and FET52, and parasitic inductances L51 and L52.
In FIG. 11, VSET1 represents direct current source, VCONT represents control signal voltage, V1 represents output voltage of the operational amplifier OP51, VOUT represents coupled voltage of transistors FET51 and FET52, Vcc represents +5 V of voltage source, Vee represents −5 V of voltage source, Vdd represents 1.5 V of voltage source, VSOA represents anode voltage, and ISOA represents current of the SOA.
The operational amplifier OP51 includes a non-inverting amplifying circuit. The operational amplifier OP51 is a high-speed operational amplifier which has an output current capacity of 300 mA or more, about a band of 1 GHz, about a slew rate of 5000 V/μs, and a settling time of about 2 ns.
The direct current source VSET1 at 0.825 V is arranged at an input terminal of the operational amplifier OP51. The operational amplifier OP51 amplifies the voltage of VSET1 UP to 1.65 V (V1 becomes 1.65 V). The drain of the transistor FET51 is connected with the output of the operational amplifier OP51.
The transistors FET51 and FET52 are high-speed transistors. The drain of the transistor FET51 is connected with the output of the operational amplifier OP51, and the source of the transistor FET51 is connected with the drain of the transistor FET52. Further, the drain of the transistor FET52 is connected with the source of the transistor FET51, and the source of the transistor FET51 is connected with ground.
Further, a connection point of the transistors FET51 and FET52 is connected with the SOA 40 (semiconductor amplifying gate switch module) via the inductances L51 and L52. The parasitic inductance L51 is in transmission line of a substrate from the connection point to the SOA 40, and the parasitic inductance L52 is in the transmission line inside the SOA 40.
CONT (control signal) turns the SOA 40 on or off. The buffer BUF52 has delay characteristics similarly to the inverter INV.
The operational amplifiers OP52 and OP53 are FET driving comparator amplifiers which drive the transistors FET51 and FET52. The operational amplifiers OP52 and OP53 have performance similar to that of the operational amplifier OP51.
When the control signal CONT is set at a HIGH level, the transistor FERT51 is turned on, and the transistor FET52 is turned on. When the transistor FET51 is turned on and the transistor FET52 is turned off, the output voltage of the operational amplifier OP51 is supplied for the SOA 40 via the transistor FET51 and the parasitic inductances L51 and L52 (the SOA 40 is turned on).
The transistor FET51 has an internal resistance of 0.5 Ω. Thus, when a current of 300 mA is applied, voltage drops by 0.15 V. Due to the voltage drop, VOUT is set at 1.5 V.
On the other hand, when the control signal CONT is set at a LOW level, the transistor FET51 is turned off, and the transistor FET52 is turned on. When transistor FET51 is turned off, and the transistor FET52 is turned on, VOUT is set at a ground-level voltage. Accordingly, current is not supplied for the SOA 40, and the SOA 40 is turned off.
There has been disclosed technology in Japanese Laid-open Patent Publication No. 2000-261508 in which feedback resistance is provided in a termination circuit using an operational amplifier to reduce power consumption and suppress reflection at a termination of a signal line, whereby errors are prevented.
In the conventional technology described above, however, ringing in the trailing edge and the rising edge cannot be suppressed, and thus the optical switch cannot be speeded up.
The ringing in the drive circuit 45 is described. FIG. 12 depicts an illustration of the ringing of the conventional drive circuit 45. In FIG. 12, VOUT represents a source voltage waveform of the transistor FET41, VSOA represents an anode voltage waveform of the SOA 40, ISOA represents a current waveform of the SOA 40 (FIG. 12 depicts the voltage waveform in “V”, and the current waveform in “A”).
The waveforms in FIG. 12 have ringing in the trailing edge. The ringing occurs when electric charge stored in junction capacitance (about 70 pF) of the SOA 40 is electrically discharged. Due to the ringing in the trailing edge, VSOA goes over 0.65 V. Accordingly, the extinction ratio of the SOA 40 becomes 58 dB or less, whereby the optical signal is affected. It takes about 5.2 ns to pass through the trailing edge including the ringing, whereby the optical switch cannot be speeded up.
On the other hand, the rising edge of VOUT causes the ringing of ISOA, and accordingly, causes the ringing of optical output of the SOA 40. An optical surge is thus caused, which may degenerate the optical transceiver. Further, the ringing causes noise on the main signal where the light overlays, whereby errors may arise. Further, it takes about 14 ns for the waveform of the ringing to return to normal, whereby speed of the rising edge becomes slow.